With semiconductor devices a multilayer wiring including a structure in which a lower wiring and an upper wiring are connected by a via is known.
The following dual damascene methods are known as techniques for forming a via and an upper wiring in the multilayer wiring. With the dual damascene methods, a hole for a via (via hole) which communicates with a lower wiring and an upper wiring trench are formed in an insulating layer, such as an interlayer insulating film, and a conductive material is embedded in the via hole and the trench.
Furthermore, the following method (via first dual damascene method) is known as one of the dual damascene methods. With the via first dual damascene method, a via hole which communicates with a lower wiring is formed first by etching, then a trench which communicates with the via hole is formed by etching, and then a conductive material is embedded in the via hole and the trench.
Japanese Laid-open Patent Publication No. 04-332152
Japanese Laid-open Patent Publication No. 2009-049034
Japanese Laid-open Patent Publication No. 2008-047582
If the dual damascene method in which a via hole that communicates with a lower wiring is formed first and in which after that a trench that communicates with the via hole is formed is adopted, the size of the via hole formed first may become larger than a desired size as a result of etching performed at the time of forming the trench.